Electronics engineer at Siemens EDA, IIT (BHU) graduate, with hands-on experience across RTL design, FPGA, emulation runtimes, and inter-process communication.
Selected projects
Python · FFmpeg · Creative Tool · 2026
VPNOOR
Designer & Implementer
A command-line tool that deliberately degrades clean video into three distinct retro/glitch looks — '2005 digital camera', 'corrupted digital', and 'absolutely destroyed' — using chained FFmpeg pipelines.
SDL3 · C/C++ · Simulation · 2026
Knights on a Board
Designer & Developer
An SDL3 framebuffer simulation inspired by Numberphile's 'Red & Black Knights' puzzle, rendering emergent movement patterns from simple per-agent rules.
C++17 · SDL3 · Convolution · 2026
ImgMixer
Designer & Implementer
A real-time image convolution playground in C++ and SDL3 — blur, Gaussian blur, emboss, Laplacian, Sobel, ridge detection, sharpen, and inversion, switchable live.
IP Design · FPGA · AXI Stream · Aug 2024
Goldsmith Division Algorithm IP
Designer & Implementer
Designed and implemented an IP block for the Goldsmith Division Algorithm on AXI Stream, achieving floating-point division in 6 cycles at 99.99% accuracy on a Pynq Z1 board.
Probability · Geometry · Nov 2024
Geometric Probability: Equidistant Point Puzzle
Problem solver
A full geometric derivation of a two-random-points probability puzzle — locus construction, sector/intersection areas, and an 8-fold symmetry reduction to a closed-form integral.
Signal Processing · Research · Jan–Mar 2024
OTFS Waveform Design
Researcher
Investigated the transition from OFDM to OTFS for next-generation wireless, improving spectral efficiency by 20% and BER performance by 30% in low-SNR conditions.
Verilog · RTL · Vivado · Aug 2023
Bubble Sort in RTL
Designer
Built a data flow model and state diagram for the Bubble Sort algorithm in Verilog, a foundational project in RTL design and simulation with Vivado.
What I believe in
I care about getting the fundamentals right — correctness first, performance second, and never shipping something I haven't actually tested. Good engineering is boring in the best way.
I like working close to the metal — kernels, emulation runtimes, RTL — but I stay curious about the layers above and below. Every internship and role has been a chance to learn a new stack from the ground up.
Background
Siemens EDA
Progressed from a summer Hardware Intern to a full-time engineer in Siemens' R&D division, working on the stability and runtime of the Veloce emulation platform.
Maintain and improve TBX-IPC (Inter-Process Communication), the core communication layer of the platform
Shipped 'tbx-session-id', a project that materially improved Veloce platform stability
Work on Questa and its runtime aspects alongside IPC responsibilities
As an intern: revamped a faulty flip-flop detection utility, adding progress reports, flop filtering, and waveform visualisation — cutting analysis time by 50%
Built strong familiarity with OS, kernel, and emulation runtime internals through this work
EPFL — LAP (Prof. Paolo Ienne)
Worked on the Dynamatic High-Level Synthesis compiler, improving buffer placement for dataflow circuits.
Improved the buffer placement algorithm focusing on MILP-based scheduling for dataflow circuits
Identified and corrected missing throughput constraints, improving accuracy of buffer insertion
Victoria University
Worked on ROS2-based navigation and mapping for the Turtlebot4 platform in a Linux/Raspberry Pi environment.
Modified ROS2 packages for Turtlebot4 navigation and mapping
Gained proficiency working with Raspberry Pi 4 in Linux environments
Organized a live demonstration of Turtlebot4 for 40+ students at the university
Skills
Programming Languages
Familiar With
Software & Tools
Interests
Education
B.Tech in Electronics & Communication Engineering (minor in Computer Science Engineering)
Indian Institute of Technology (BHU), Varanasi · 2021 – 2025
CGPA 9.50/10 · Department Rank 3/146
About
I studied Electronics & Communication Engineering at IIT (BHU), with a minor in Computer Science, and found myself drawn to the layer where hardware meets software — emulation runtimes, RTL, and the systems code that ties it all together.
I've worked across a Siemens EDA production platform, an EPFL compiler research lab, and a robotics lab at Victoria University — going from summer intern to full-time engineer along the way. I bring curiosity, attention to detail, and a habit of actually testing what I ship.
Based in India. Open to interesting engineering problems.
I'd love to talk shop or work on something together, Send Hi